Intel Senior Manager Design Verification in San Jose, California

Job Description

As a Senior Design Verification Manager for high speed digital design you will work closely with an energetic design engineering team and management to develop next generation FPGA platforms for the data center and networking markets. You will manage the verification team to verify next generation FPGA with high speed serial protocols such as PCIe, UPI, Ethernet, Memory controller using state of the art technologies. You will work to drive innovation and consistent methodologies as you solve challenging problem, while pushing the technology boundaries for FPGA. You will manage the team to create verification architecture, test plan, test bench execute test-plan and coverage closure. You will be responsible for design verification of a complex design while creating a culture of industry standard best practices and methodologies. You will be responsible for carrying out IP, IP subsystem and system level verification efforts in support of Intel PSG's FPGA product development. In addition, you will be responsible for supporting silicon bring up activities.

Qualifications

The successful candidate's minimum qualifications will include the following: o BSEE or MSEE with 10+ years of verification experience in FPGA, ASIC or custom IC designs o Experience with high-speed transceiver protocols PCI Express is must and UPI is desirableo Minimum 2+ years of Management experience Strong background in System Verilog, VMM/UVM and C/C++ o Strong understanding of Hardware Design, Verification and Validation Principleso Strong experience with Verilog and System Verilog design of complex IP blocks working with high speed design. o Strong background in design verification, Knowledge of UVM based methodologies preferred o Strong background in the following verification disciplines: test bench architecture, test case development, functional coverage, coverage collection and analysis o Demonstrated ability to create and document verification planso Experience with high-speed memory protocols including DDR3/4 and HBM2 is desirable o Experience with microcontroller subsystem verification is desirable o Experience with formal verification methods property checking is desirableo Experience verifying design-for-test DFT logic is desirable o Strong verbal and written communication skills

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.

Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.