GLOBALFOUNDRIES ASIC IP Development – PLL Analog Design in United States

Summary of Rol e: The ASIC IP Phase Lock Loop (PLL) Development team is seeking an ASIC analog designer:

GLOBAL FOUNDRIES is looking for an ASIC analog phase lock loop designer to support the ASIC IP PLL development team in providing world class PLL designs for advanced technologies such as 14nm and 7nm. This position will be required to both assist other engineers on the team in PLL and PLL sub circuit designs as well as eventually own/lead a design project(s). This includes schematic design, simulation, providing guidance to mask/layout designers and verification of the design. The candidate will need to be successful in a design environment based in Cadence Spectre executing circuit design and simulation of PLL circuitry (examples of design circuitry includes: Voltage Control Oscillators (VCO), Phase Frequency Detectors, Charge Pump, Filters, Dividers, etc.), current references (SINK, SRC, PTAT), voltage references (Bandgap, Altref, Voltage Regulators, VBOOST), and clock distribution, receiver, etc. The ideal candidate will have some experience (albeit limited) in 14nm and/or 7nm FinFET Technology and be able to meet both internal and customer design schedules.

Essential Responsibilities :

  • Perform functional simulations for various PLL sub-circuits

  • Perform cross section simulations for PLL

  • Perform NOISE (Rj and Dj – random and deterministic jitter) analysis for PLL

  • Assist the team lead to perform PLL loop level stability analysis and phase noise analysis

  • Knowledge on Spectre, SpectreRF, APS EMIR, MDL simulations

  • Knowledge on Fx14 finFET layout

  • Perform functional simulations for various Voltage Regulator sub-circuits

  • Perform cross section simulations for PLL sub circuits (e.g. voltage regulators)

  • Perform AC analysis, PSRR and stability analysis on PLL sub circuits

  • Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs

    Alternative work locations: Santa Clara, CA; Raleigh, NC; Austin, TX; Rochester, MN;

    Required Qualifications :

    ● Education – Bachelor Degree in Science or Engineering

    ● Experience – 0-2 years in analog design development

    ● Travel – (% of travel required) less than 5%

    ● Language Fluency – Fluent in English Language – written & verbal

    If you need a reasonable accommodation for any part of the employment process, please contact us by email at usaccommodations@globalfoundries.com and let us know the nature of your request and your contact information. Requests for accommodation will be considered on a case-by-case basis. Please note that only inquiries concerning a request for reasonable accommodation will be responded to from this email address.

    An offer of employment with GLOBAL FOUNDRIES is conditioned upon the successful completion of a background check and drug screen, as applicable, and subject to applicable laws and regulations.

    GLOBALFOUNDRIES is an Equal Opportunity/Affirmative Action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, gender, sexual orientation, gender identity, national origin, disability, or protected Veteran status.

Title: ASIC IP Development – PLL Analog Design

Location: null

Requisition ID: 17006148